1. Field of the Invention
The present invention relates to optimization of a test, and more particularly, to a decoder for reducing a test time for detecting defective switches in a digital-to-analog converter.
2. Description of the Related Art
A digital-to-analog converter (DA converter) is a device for converting a discrete digital signal used in contemporary electronic systems to a continuous analog signal which a human can perceive. The DA converter essentially includes a plurality of direct current voltage sources having generally different voltage levels, and a decoder portion having a plurality of switches for switching these voltage sources.
FIG. 1 illustrates a conventional decoder using NMOS transistors as switches.
Referring to FIG. 1, the conventional decoder includes eight direct current voltage sources (VL1 through VL8) having different voltage levels, a plurality of NMOS transistors (MN1 through MN24) which are connected to the eight direct current voltage sources (VL1 through VL8) in series in groups of three and used as switches, three digital signals (D0 through D2) for controlling the plurality of NMOS transistors (MN1 through MN24), and three inverters 11, 12, 13 for inverting the 3 digital signals, respectively.
When the three digital signals (D0 through D2) are all logic high, the three NMOS transistors (MN1 through MN3) turn on, and the direct current voltage source (VL1) is transmitted to an output terminal (VLOUT). When the three digital signals (D0 through D2) are all logic low, three NMOS transistors (MN22 through MN24) turn on, and the direct current voltage source (VL8) is transmitted to the output terminal (VLOUT).
FIG. 2 illustrates a conventional decoder using PMOS transistors as switches. Referring to FIG. 2, the conventional decoder includes eight direct current voltage sources (VH1 through VH8) having different voltage levels, a plurality of PMOS transistors (MP1 through MP24) which are connected to the eight direct current voltage sources (VH1 through VH8) in series in groups of three, and used as switches, three digital signals (D0 through D2) for controlling the plurality of PMOS transistors, and three inverters (21 through 23) for inverting the three digital signals (D0 through D2).
When the three digital signals (D0 through D2) are all logic low, three PMOS transistors (MP1 through MN3) turn on, and the direct current voltage source (VH1) is transmitted to an output terminal (VHOUT). When the three digital signals (D0 through D2) are all logic high, three PMOS transistors (MP22 through MP24) turn on, and the direct current voltage source (VH8) is transmitted to the output terminal (VHOUT).
Referring to FIGS. 1 and 2, one of the eight direct current voltage sources is transmitted to the output terminal (VLOUT) depending on a logic state of the three digital signals (D0 through D2), and a total of three digital signals (D0 through D2) and 24 switches (MN1 through MN24 or MP1 through MP24) are required for selecting and outputting eight analog voltage levels. If there are defects in the switches, the decoder malfunctions.
An NMOS transistor or a PMOS transistor is used as a switch, or a transmission gate combining the NMOS transistor and PMOS transistor is used. The probability of occurrence of a malfunction increases as the number of switches used increases. In order to detect malfunctioning switches, all switches connected to the direct current voltage sources must be tested. A conventional method for testing the switches, in which a switch connected to a direct current voltage source in series is tested one at a time, has many shortcomings in terms of time and economic efficiency.
To address the above limitations, it is an objective of the present invention to provide a decoder including a test controlling portion which turns on all switches in response to an externally applied test order signal, and detects all defective switches simultaneously by applying a specific pattern.
Accordingly, to achieve the above objective, according to a first preferred embodiment of the present invention, a decoder including a switch controlling portion and a switching portion is provided.
The switch controlling portion receives a plurality of digital input signals having digital information related to an analog output signal and at least one test order signal having data indicating a normal mode of operation or a test mode of operation, outputs as control signals the plurality of digital input signals and inverted signals of the plurality of digital input signals when the test order signal orders a normal mode, and outputs as control signals the plurality of digital input signals and signals having the same phase as the plurality of digital input signals when the test order signal orders a test mode.
The switch portion includes a plurality of switches connected to the same number of direct current voltage source inputs having different voltage levels in series, and switches the plurality of direct current voltage sources as a function of the plurality of control signals of the switch controlling portion.
The switch controlling portion preferably includes a plurality of mode selecting circuits. The plurality of mode selecting circuits output an inverted signal of each of the digital input signals when the test order signal orders a normal mode, and output a signal having the same phase as each of the digital input signals when the test order signal orders a test mode. The plurality of mode selecting circuits include NAND gates, in which one input is connected to one signal of the plurality of digital input signals, and the other input is connected to at least one test order signal. Each of the switches of the switch portion is realized as an NMOS transistor.
To achieve the above objective, according to a second preferred embodiment of the present invention, there is provided a decoder, in which the plurality of switches of the switch portion is realized with PMOS transistors instead of NMOS transistors, and the plurality of mode selecting circuits are replaced with NOR gates having one end connected to one signal of the plurality of digital input signals, and the other end connected to at least one test order signal, instead of NAND gates.